The internal functions of recent large-scale integrated circuits have become more and more sophisticated. Since large-scale integrated circuits contain therein a combinational logic circuit and a plurality of functional macrocircuits having a specified function, this dramatically increases the number of circuit elements contained in large-scale integrated circuits. Memory, DAC (digital-to-analog converter), or the like component is used as the functional macrocircuit. As the internal function of large-scale integrated circuits becomes elaborate, the functional testing thereof becomes difficult to perform. In testing a large-scale integrated circuit for its functions, both the controllability of externally controlling portions to be tested and the ovservability of externally observing a result of the test play an important role.
A basic manner of the function test is a test that is carried out using a specified test vector through test buses disposed to provide external control or observation of the internal state of portions of a large-scale integrated circuit. Scan testing is known as a function test technique for testing combinational logic circuits to achieve a high test coverage with a less test vector quantity. Such a scan test is composed of scan-in and scan-out, the scan-in using a test bus for the provision of data to the inside of a large-scale integrated circuit and the scan-out using another test bus for the observation of the data. On the other hand, macro testing is known as a technique for testing functional macrocircuits, in which the processing of inputting and outputting data is sequentially performed on a functional macrocircuit according to a given algorithm and the value of an output obtained is compared with a specified expected value for determining whether the functional macrocircuit is functioning correctly.
The above-described organization, however, suffers the following drawbacks. As the level of integration of random logical circuits becomes higher, the number of circuit elements increases thereby increasing the number of scan buses. As a result, both the number of scan-in terminals and the number of scan-out terminals increase. Additionally, not only because the number of functional macrocircuits is made to increase for improvements in performance, but also because of an expansion in address bus width and data bus width in cases where functional macrocircuits are formed by a memory, the numbers of macro-in and macro-out terminals increase. This requires a great number of input and output (I/O) terminals for test operation (i.e., scan-in terminals, scan-out terminals, macro-in terminals, and macro-out terminals), in addition to input and output (I/O) terminals for normal operation, therefore leading to an increase in chip area. With the speed-up of normal operations in semiconductor integrated circuit, it becomes necessary to achieve a reduction of the signal delay in I/O terminals for normal operation. In order to meet such a requirement as to the speed-up of normal operations, it is necessary to provide I/O terminals for normal operation capable of achieving a minimum signal delay independently of I/O terminals for test operation. This, however, results in a further increase in chip area because the total number of I/O terminals increases.
If I/O terminals are shared between normal operation and test operation, this will control the increase in chip area. However, in such a case, a route switch means of performing switching between a route at normal operation time and another at test operation time and another route switch means of performing switching between a route for scan test and another for macro test must be disposed on the input and output sides. This is a bar to the speed-up of operations.